Optimum design of FIR switched-capacitor decimators using low-gain amplifiers

Access Full Text

Optimum design of FIR switched-capacitor decimators using low-gain amplifiers

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Strategies are presented for the optimum design of FIR switched-capacitor decimators using low-gain amplifiers. It is illustrated that one such new design improves the amplitude response of an existing circuit when the DC gain of the amplifiers is as low as 100.

Inspec keywords: active networks; switched capacitor networks

Other keywords: FIR switched-capacitor decimators; DC gain; optimum design; amplitude response; low-gain amplifiers

Subjects: Active filters and other active networks

References

    1. 1)
      • K. Haug , F. Maloberti , G.C. Temes . Switched-capacitor integrators with low finite-gain sensitivity. Electron. Lett. , 1156 - 1157
    2. 2)
      • J.E. Franca . Non-recursive polyphase switched-capacitor decimators. IEEE Trans. , 877 - 887
    3. 3)
      • Y. Tsividis . Principles of operation of switched-capacitor circuits. Proc. IEEE , 926 - 940
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19880130
Loading

Related content

content/journals/10.1049/el_19880130
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading