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High-speed and high-coding-gain Viterbi decoder with low power consumption employing SST (scarce state transition) scheme

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Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pe performance (4.2 dB net coding gain at Pe = 1 × 10-6), drastic reduction of power consumption and number of gates with low development costs.

References

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      • S. Kubota , T. Kohri , S. Kato . A scarce state transition type Viterbi decoder. Trans. IECE Jpn. , 38 - 45

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content/journals/10.1049/el_19860334
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