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Switching circuits for yield-enhancement of an array chip

Switching circuits for yield-enhancement of an array chip

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McCanny and McWhirter describe a method for enhancing the yield of a bit-level systolic array chip. A limitation of their approach is that all the configuration circuitry must work. We have examined alternative approaches which tolerate some defects in this circuitry and find one scheme in particular which turns out to be much more effective.

Inspec keywords: cellular arrays; switching circuits; digital integrated circuits

Other keywords: switching circuits; bit-level systolic array chip; configuration circuitry

Subjects: Digital electronics; Semiconductor integrated circuits

References

    1. 1)
      • Wood, D., Evans, R.A., Wood, K.: `An 8-bit serial convolver chip based on a bit level systolic array', IEEE Custom Integrated Circuits Conference, May 1983, p. 256–261.
    2. 2)
      • W.R. Moore . Fault detection and correction in array computers for image processing. IEE Proc. E, Comput. & Digital Tech. , 229 - 234
    3. 3)
      • Kung, H.T., Lam, M.S.: `Fault-tolerance and two-level pipelining in VLSI systolic arrays', MIT Conference on advanced research in VLSI, January 1984.
    4. 4)
      • W.R. Moore , M.J. Day . Yield-enhancement of a large systolic array chip. Microelectron. & Reliab.
    5. 5)
      • J.V. McCanny , J.G. McWhirter . Yield enhancement of bit level systolic array chips using fault-tolerance techniques. Electron. Lett. , 525 - 527
    6. 6)
      • W.R. Moore . A review of fault-tolerant techniques for the enhancement of integrated circuit yield. GEC J. Res. , 1 - 15
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