Some results of testing m.o.s. transistors at elevated temperatures

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Some results of testing m.o.s. transistors at elevated temperatures

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© The Institution of Electrical Engineers
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Some results of testing p channel enhancement-type m.o.s. transistors with negative gate bias at elevated temperatures are given. Such a treatment causes an initial temporary decrease in the threshold voltage Vth, followed by a significant increase of this parameter which is dependent on bias, temperature and treatment time. It is thought that these changes in Vth and changes in other device parameters are due to high-temperature polarisation and then depolarisation of the phosphosilicate-glass stabilisation layer, as well as the slow trapping in silicon dioxide and creation of new surface states at the silicon-silicon-dioxide interface.

Inspec keywords: characteristics measurement; field effect transistors; semiconductor device testing

Other keywords: p channel enhancement type; elevated temperatures; testing; transistors with negative gate; metal oxide semiconductor

Subjects: Other electric variables measurement; Other field effect devices

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