1/f noise in gate-controlled planar silicon diodes

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1/f noise in gate-controlled planar silicon diodes

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© The Institution of Electrical Engineers
Published

Low-frequency excess noise in planar bipolar silicon devices was investigated by means of gate-controlled n+−p diodes. Within the range of parameter values covered in this investigation, it was found that the noise-power maxima invariably occur at gate bias voltages leading to depletion of majority carriers at the surface of the high-resistivity side of the p–n junction.

Inspec keywords: noise

Subjects: Junction and barrier diodes

References

    1. 1)
      • A.S. Grove , D.J. Fitzgerald . Surface effects on p–n junctions: characteristics of surface space-charge regions under non-equilibrium conditions. Solid-State Electronics , 783 - 806
    2. 2)
      • C.T. Sah , F.H. Hielscher . Evidence of the surface origin of the 1/f noise. Phys. Rev. Letters , 956 - 957
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