A novel capacitor mismatch calibration method is presented to compensate the capacitor mismatches in a successive approximation register (SAR) ADC. The method features a new weight-balancing split capacitive DAC which allows automatic extraction and calibration of the capacitor mismatches by itself. As a result, the ADC's resolution can be substantially improved with minimum area and power penalty. The calibration method was verified and implemented in a 14 bit, 10 kS/s SAR ADC, fabricated in a 0.13 µm standard CMOS process. The measured signal-to-noise-plus-distortion and spurious-free dynamic range are 72.7 and 86 dB after calibration with 13.6 and 21.8 dB improvements, respectively. The total power consumption is 15.2 µW at a 1.2 V supply voltage.