© The Institution of Engineering and Technology
A 2 × time-interleaved 1 GS/s 7b ADC is presented, which uses pulse-width modulation and time domain quantisation for digitisation and is designed for wide channel bandwidths available at mm-wave frequencies. The area, resolution and power performance of the highly digital time-domain architecture is likely to scale with technology. The prototype ADC achieves 5.24 ENOB at a Nyquist rate while consuming 5.22 mW of power, resulting in a fJ/conversion step in TSMC's 65 nm GP CMOS process.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2018.5393
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