Compact modelling for quantum confinement for InGaAs nanowire gate all around MOSFET

A. Abdelmoneam; B. Iñiguez

Compact modelling for quantum confinement for InGaAs nanowire gate all around MOSFET

View Fulltext

Author(s): A. Abdelmoneam¹ and B. Iñiguez²
- Affiliations: 1: Nanotechnology Engineering Department , Arab Academy for Science and Technology , Cairo , Egypt ;
  2: Department of Electrical, Electronic Engineering and Automation , URV , Tarragona , Spain
Source: Volume 54, Issue 23, 15 November 2018, p. 1348 – 1350
DOI: 10.1049/el.2018.5075 , Print ISSN 0013-5194, Online ISSN 1350-911X

Received 25/04/2018, Published 10/10/2018

In this Letter, a compact equation for calculating energy sub-bands inside III–V gate all around nanowire MOSFET is developed taking into consideration the penetration of the wave function into the gate oxide and the effective mass discontinuity at the semiconductor–oxide interface. The values of the sub-band energies result from solving Schrodinger's equation in cylindrical coordinates is expressed in Bessel functions. The authors use an approximation for Bessel functions with the introduction of one fitting parameter. The results show very good agreement with self-consistent Schrodinger–Poisson solver data.

References

1. 1)
  - 1. del Alamo, J.A.: ‘Nanometre-scale electronics with III–V compound semiconductors’, Nature, 2011, 479, pp. 317–323 (doi: 10.1038/nature10677).
2. 2)
  - 5. Roy, A.S., Mundanai, S.P., Basu, D., et al: ‘Compact model for ultrathin low electron effective mass double gate MOSFET’, Trans. Electron Devices, 2014, 61, (2), pp. 308–313 (doi: 10.1109/TED.2013.2290779).
3. 3)
  - 6. Mudanai, S., Roy, A.S., Kotlyar, R., et al: ‘Capacitance compact model for ultrathin low-electron-effective-mass materials’, Trans. Electron Devices, 2011, 58, (12), pp. 4204–4211 (doi: 10.1109/TED.2011.2168529).
4. 4)
  - 2. Alamo, J.A.d., et al: ‘III–V MOSFETs for future CMOS’. 2015 IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), New Orleans, LA, USA, October 2015.
5. 5)
  - 2. Colinge, J.-P.: ‘Multi-gate SOI MOSFETs’, Microelectron. Eng., 2007, 84, pp. 2071–2076 (doi: 10.1016/j.mee.2007.04.038).
6. 6)
  - 8. Ganeriwala, M.D., Yadav, C., Riuz, F.G., et al: ‘Modeling of quantum confinement and capacitance in III–V gate-all-around 1-D transistors’, Trans. Electron Devices, 2017, 64, (12), pp. 4889–4896 (doi: 10.1109/TED.2017.2766693).
7. 7)
  - 3. Natarajan, S., et al: ‘A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm SRAM cell size’. 2014 IEEE Int. Electron Devices Meeting, San Francisco, CA, USA, December 2014.
8. 8)
  - 7. Marin, E.G., Tienda-Luna, I.M., Godoy, A., et al: ‘Analytic potential and charge model for III-V surrounding gate metal-oxide-semiconductor field-effect transistors’, J. Appl. Phys., 2012, 112, (8), p. 084512 (doi: 10.1063/1.4759275).
9. 9)
  - 10. Kim, J., Fischetti, M.V.: ‘Electronic band structure calculations for biaxially strained Si, Ge, and III–V semiconductors’, J. Appl. Phys., 2010, 108, (1), p. 013710 (doi: 10.1063/1.3437655).
10. 10)
  - 9. Watson, G.N.: ‘A treatise on the theory of Bessel functions’ (Cambridge University Press, Cambridge, UK, 1944).

Correspondence

This article has following corresponding article(s):

in brief

Login

Not registered yet?

Share

Tools

Login to add to favourites

Key

Compact modelling for quantum confinement for InGaAs nanowire gate all around MOSFET

References

Related content