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access icon free Fully-VCO-based 0-2 MASH CT ΔΣ ADC

  • Author(s): Xinpeng Xing 1 ; Peng Zhu 2 ; Hui Liu 3 ; Georges Gielen 3
    • View affiliations
  • Source: Volume 54, Issue 17, 23 August 2018, p. 1018 – 1020
    DOI:  10.1049/el.2018.1284 , Print ISSN 0013-5194, Online ISSN 1350-911X
© The Institution of Engineering and Technology
Received 12/04/2018, Published 31/07/2018

A fully-voltage-controlled oscillator (VCO)-based continuous-time (CT) Delta-Sigma (ΔΣ) analogue-to-digital converter (ADC) is reported, implementing second-order noise shaping without any analogue integrators. Traditional power-hungry front-end analogue integrator is replaced by a highly-digital power-efficient VCO-based integrator, which is constructed by a VCO, a phase detector and a charge pump. The quantisation is executed by a VCO-based quantiser with intrinsic noise shaping. Taking advantage of the mostly-digital and high-order structure, a spurious-free dynamic range of 74 dB and a figure-of-merit of 52 fJ/step over a 40 MHz bandwidth are achieved by a 0-2 multi-stage shaping (MASH) demonstration in 40 nm CMOS.

Inspec keywords: quantisation (signal); phase detectors; CMOS digital integrated circuits; delta-sigma modulation; charge pump circuits; analogue-digital conversion; voltage-controlled oscillators

Other keywords: high-order structure; intrinsic noise shaping; CMOS process; charge pump; VCO-based quantiser; multistage shaping demonstration; figure-of-merit; analogue integrators; fully-voltage-controlled oscillator-based continuous-time delta-sigma analogue-to-digital converter; highly-digital power-efficient VCO-based integrator; VCO; spurious-free dynamic range; second-order noise shaping; phase detector; traditional power-hungry front-end analogue integrator; fully-VCO-based 0-2 MASH CT ΔΣ ADC; size 40.0 nm

Subjects: Modulators, demodulators, discriminators and mixers; Oscillators; A/D and D/A convertors; CMOS integrated circuits; A/D and D/A convertors

References

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      • 2. Reddy, K., Rao, S., Inti, R., et al: ‘A 16 mW 78 dB-SNDR 10 MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer’. ISSCC Dig. Tech. Papers, February 2012, pp. 152–153.
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      • 3. Yoon, Y., Lee, K., Wang, P., et al: ‘A purely-VCO-based single-loop high-order continuous-time ΣΔ ADC’. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Melbourne VIC, Australia, June 2014, pp. 926–929.
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