access icon free 40 Gbps 4-level pulse amplitude modulation closed-loop decision-feedback equaliser with high-speed comparator in 55 nm CMOS technology

© The Institution of Engineering and Technology
Received 06/04/2018, Published 14/05/2018

A 40 Gbps 4-tap 4-level pulse amplitude modulation closed-loop decision feedback equaliser (DFE) is proposed. The DFE adopts a novel high-speed comparator to resolve the critical timing constraints of the first tap. The comparator decreases the slicing delay by shortening the gap between initial and target voltages. Compared with the existing closed-loop DFE designs, the proposed scheme relieves timing constraints without complex clock distribution circuits and extra area. Simulations based on the RF-MOS model verify that the delay of the comparator is improved by 32.8% and the output swing is increased by more than 2.8 times. The proposed DFE which can compensate −9.5 dB channel loss is designed in 55 nm CMOS technology. The power consumption is 67 mW from a 1.2 V supply and the circuit occupies an active area of 0.021 mm2, achieving 1.68 pJ/bit energy efficiency.

Inspec keywords: CMOS analogue integrated circuits; integrated circuit modelling; decision feedback equalisers; pulse amplitude modulation; comparators (circuits)

Other keywords: closed-loop DFE designs; size 55 nm; bit rate 40 Gbit/s; RF-MOS model; voltage 1.2 V; power consumption; power 67 mW; critical timing constraints; 4-level pulse amplitude modulation closed-loop decision-feedback equaliser; channel loss; slicing delay; loss -9.5 dB; high-speed comparator; CMOS technology

Subjects: Analogue circuit design, modelling and testing; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Other analogue circuits

References

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      • 1. Jaussi, J., Balamurugan, G., Hyvonen, S., et al: ‘A 205 mW 32 Gb/s 3-tap FFE/6-tap DFE bidirectional serial link in 22 nm CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2014, pp. 440–441, doi: 10.1109/ISSCC.2014.6757504.
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      • 2. Lu, Y., Alon, E.: ‘A 66 Gb/s 46 mW 3-tap decision-feedback equalizer in 65 nm CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2013, pp. 30–31, doi: 10.1109/ISSCC.2013.6487623.
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      • 5. Lm, J., Freitas, D., Roldan, A., et al: ‘A 40-to-56 Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16 nm FinFET’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2017, pp. 114–115, doi: 10.1109/ISSCC.2017.7870287.
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      • 3. Tang, L., Gai, W., Shi, L., et al: ‘A 32 Gb/s 133 mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65 nm CMOS’. ISSCC Digest of Technical Papers, San Francisco, USA, February 2018, pp. 114–115, doi: 10.1109/ISSCC.2018.8310210.
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