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0.75 V 2.6 GHz digital bang–bang PLL with dynamic double-tail phase detector and supply-noise-tolerant g m-controlled DCO

0.75 V 2.6 GHz digital bang–bang PLL with dynamic double-tail phase detector and supply-noise-tolerant g m-controlled DCO

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A compact low-supply-voltage yet low-noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double-tail latch which enables high time-to-voltage gain and low input-referred noise under tight power-supply headroom. The ring-based digitally controlled oscillator (DCO) is made of multiple g m-controlled delay units and a constant-g m-biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in-band phase noise of −105 dBc/Hz.

References

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      • B. Kim , S. Kundu , C.H. Kim .
        8. Kim, B., Kundu, S., Kim, C.H., et al: ‘A 0.4–1.6 GHz spur-free bang–bang digital PLL in 65 nm with a D-flip-flop based frequency subtractor circuit’. Proc. Symp. VLSI Circuits, Kyoto, Japan, June 2015, pp. 140141.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.4168
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