access icon free Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS

The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8 × 8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance.

Inspec keywords: low-power electronics; multiplying circuits; CMOS logic circuits; logic design; power consumption

Other keywords: binary-to-2's complement converter; 2:1 MUX; unique optimised stage-1 architecture; size 90.0 nm; battery powered applications; digital multiplier circuit; CPU portable applications; microelectronic implementations; adder-subtractor; CPU; graphic processing unit; power consumption; CMOS technology; low-power-delay-product radix-4 8 × 8 Booth multiplier; digital signal processing; voltage 1.2 V

Subjects: Digital circuit design, modelling and testing; Logic design methods; Logic circuits; Logic and switching circuits; CMOS integrated circuits

References

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      • 4. Qian, L., Wang, C., Liu, W., et al: ‘Design and evaluation of an approximate wallace-booth multiplier’. IEEE Int. Symp. Circuits and Systems (ISCAS), Montreal, QC, Canada, May 2016, pp. 19741977.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3996
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