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1887

access icon free Five to 25 Gb/s continuous time linear equaliser with transversal architecture

© The Institution of Engineering and Technology
Received 15/08/2017, Published 14/11/2017

Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid mean-square-error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB-loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10−12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data-rate and channel loss.

Inspec keywords: gradient methods; mean square error methods; CMOS integrated circuits; equalisers

Other keywords: bit rate 5 Gbit/s to 25 Gbit/s; paraboloid mean square-error surface; transceiver; loss 20 dB; size 28 nm; power 17 mW; continuous time linear equaliser; gradient descent algorithm; transversal architecture; BER; backplane serial link; CMOS technology; CTLE; voltage 1 V

Subjects: Optimisation techniques; Interpolation and function approximation (numerical analysis); CMOS integrated circuits; Communication channel equalisation and identification; Linear algebra (numerical analysis)

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3120
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