http://iet.metastore.ingenta.com
1887

Five to 25 Gb/s continuous time linear equaliser with transversal architecture

Five to 25 Gb/s continuous time linear equaliser with transversal architecture

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid mean-square-error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB-loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10−12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data-rate and channel loss.

References

    1. 1)
      • Y.M. Ying , S.I. Liu .
        1. Ying, Y.M., Liu, S.I.: ‘A 20 Gb/s digitally adaptive equalizer/DFE with blind sampling’. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, February 2011, pp. 444445.
        . IEEE Int. Solid-State Circuits Conf. , 444 - 445
    2. 2)
    3. 3)
      • H.-Y. Joo , K.-S. Ha , L.-S. Kim .
        3. Joo, H.-Y., Ha, K.-S., Kim, L.-S.: ‘Data pattern-tolerant adaptive equalizer using spectrum balancing method’. Proc. IEEE Symp. VLSI Circuits, 2009, pp. 220221.
        . Proc. IEEE Symp. VLSI Circuits , 220 - 221
    4. 4)
      • W.S. Kim , C.K. Seong , W.Y. Choi .
        4. Kim, W.S., Seong, C.K., Choi, W.Y.: ‘A 5.4 Gb/s adaptive equalizer using asynchronous-sampling histograms’. IEEE Int. Solid-State Circuits Conf., February 2011, pp. 358359.
        . IEEE Int. Solid-State Circuits Conf. , 358 - 359
    5. 5)
      • Y.-F. Lin , C.-C. Lee , J.-Y. Max .
        5. Lin, Y.-F., Lee, C.-C., Max, J.-Y., et al: ‘A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting’. Proc. Asian Solid-State Circuits Conf. (ASSCC), November 2014, pp. 273276.
        . Proc. Asian Solid-State Circuits Conf. (ASSCC) , 273 - 276
    6. 6)
    7. 7)
      • J.E. Proesel , T.O. Dickson .
        7. Proesel, J.E., Dickson, T.O.: ‘A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45 nm SOI CMOS’. Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, USA, August 2011, pp. 206207.
        . Proc. IEEE Symp. VLSI Circuits , 206 - 207
    8. 8)
      • K. Jung , A. Amirkhany , K. Kaviani .
        8. Jung, K., Amirkhany, A., Kaviani, K.: ‘A 0.94 mW/Gb/s 22 Gb/s 2-tap partial-response DFE receiver in 40 nm LP CMOS’. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, February 2013, pp. 4243.
        . IEEE Int. Solid-State Circuits Conf. , 42 - 43
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3120
Loading

Related content

content/journals/10.1049/el.2017.3120
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address