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access icon free High-gain and power-efficient dynamic amplifier for pipelined SAR ADCs

A new power-efficient dynamic residue amplifier for pipelined successive-approximation-register (SAR) ADCs is presented. A complementary input pair and a reference level detection technique are proposed to improve the performance of the dynamic amplifier. At a 400 MS/s sampling rate, the proposed amplifier achieves a gain of 16. The input referred noise is 57.2 μV and the total harmonic distortion is –57.1 dB. The power consumption of the proposed amplifier is 55.6 μW in 28 nm CMOS technology.

References

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      • 4. Malki, B., Verbruggen, B., Wambacq, P., et al: ‘A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC’. Proc. IEEE ESSCIRC, Venice Lido, Italy, September 2014, pp. 215218.
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      • 1. Lin, J., Miyahara, M., Matsuzawa, A.: ‘A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique’. Proc. IEEE Int. Symp. Circuits and Systems, Rio de Janeiro, Brazil, May 2011, pp. 2124.
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      • 3. Lin, J., Miyahara, M., Matsuzawa, A.: ‘An ultra-low-voltage 160 MS/s 7 bit interpolated pipeline ADC using dynamic amplifier’. Proc. IEEE Custom Integrated Circuits Conf. (CICC), San Jose, USA, September 2013.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.3041
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content/journals/10.1049/el.2017.3041
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