Hardware-efficient multi-channel digital sigma-delta modulator
A method for implementing a hardware-efficient multi-channel digital sigma-delta modulator is presented for processing field sequential multiple inputs. Compared to a conventional one, which processes the inputs in a time-multiplexed manner without sharing integrator memory for the multiple sequential inputs, the proposed method significantly reduces the number of storage bits in the integrator memory by partially sharing the integrator memory for the inputs. Simulation results on modulator noise power spectral density and overall signal-to-noise ratio match well with those based on quantitative noise analysis.
