Self-aligned graphene transistor

Self-aligned graphene transistor

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A novel self-aligned (SA) graphene FET (GFET) with small access resistance is fabricated. Only one photolithography is needed to define the gate and high gate capacitive efficiency is obtained using a metal gate-stack. In addition, damages to graphene resulting from the plasma are avoided. The cap metal layer is used as an etch stop layer and the etched stem metal layer is used as a support layer, which leads to the simplification of the fabrication process and the formation of the SA structure. Based on the same gate length (3 µm), the normalized G m of GSA-GFET is 8 times larger than the reported SA-GFET. Compared with the non-SA-GFET, the contact resistance of the SA-GFET is reduced by 50% and G m is 3.2 times improved.


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