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1887

access icon free Energy-efficient higher-side-reset-and-set switching scheme for SAR ADC

A high energy-efficiency higher-side-reset-and-set (HSRS) switching scheme for a successive approximation register (SAR) ADC is presented, which consumes zero switching energy for the decision of the first two most significant bits without using any auxiliary circuit. The proposed HSRS scheme achieves 92.2% savings in switching energy and 50% reduction in total capacitance compared with a conventional SAR.

References

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      • 4. Tai, H.-Y., Hu, Y.-S., Chen, H.-W., et al: ‘A 0.85 fJ/conversion step 10b 200 kS/s subranging SAR ADC in 40 nm CMOS’. IEEE ISSCC Digest Technical Papers, San Francisco, CA, USA, February 2014, pp. 196197.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.2186
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content/journals/10.1049/el.2017.2186
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