© The Institution of Engineering and Technology
The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.
References
-
-
1)
-
6. Canright, D., Batina, L.: ‘A very compact ‘perfectly masked’ S-Box for AES’, Springer Lect. Notes Comput. Sci., 2008, 5037, pp. 446–459 (doi: 10.1007/978-3-540-68914-0_27).
-
2)
-
4. Hamalainen, P., Alho, T., Hannikainen, M., et al: ‘Design and implementation of low-area and low-power AES encryption hardware core’. EUROMICRO Conf. Digital System Design (DSD), Dubrovnik, Croatia, August 2006, pp. 577–583.
-
3)
-
11. Dofe, J., Frey, J., Yu, Q.: ‘Hardware security assurance in emerging IoT applications’. IEEE Int. Symp. Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 2050–2053.
-
4)
-
12. Ishibashi, K., Sugii, N., Kamohara, S., et al: ‘A perpetuum mobile 32 bit CPU on 65 nm SOTB CMOS technology with the reverse-body-bias assisted sleep mode’, IEICE Trans. Electron., 2015, E98-C, (7), pp. 536–543 (doi: 10.1587/transele.E98.C.536).
-
5)
-
3. Canright, D.: ‘A very compact S-box for AES’. Int. Workshop on Cryptology Hardware and Embedded Systems, Edinburgh, UK, September 2005, pp. 441–455.
-
6)
-
2. Satoh, A., Morioka, S., Takano, K., et al: ‘A compact Rijndael hardware architecture with S-box optimization’. Int. Conf. Theory and Application of Cryptology and Information Security, Gold Coast, Australia, December 2001, pp. 239–254.
-
7)
-
13. Hoang, V.-P, Dao, V.-L., Pham, C.-K.: ‘An ultra-low power AES encryption core in 65 nm SOTB CMOS process’. Int. SoC Design Conf. (ISOCC), Jeju, Japan, September 2016, pp. 89–90.
-
8)
-
7. Mathew, S., Satpathy, S., Suresh, V., et al: ‘340 mV–1.1 V, 289 Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22 nm tri-gate CMOS’, J. Solid-State Circuits, 2014, 50, (4), pp. 1048–1058 (doi: 10.1109/JSSC.2014.2384039).
-
9)
-
9. Zhao, W., Ha, Y., Alioto, M.: ‘AES architectures for minimum-energy operation and silicon demonstration in 65 nm with lowest energy per encryption’. IEEE Int. Symp. Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1–4.
-
10)
-
8. Good, T., Benaissa, M.: ‘692 nW advanced encryption standard (AES) on a 0.13 µm CMOS’, Trans. Very Large Scale Integr. Syst., 2010, 18, (12), pp. 1753–1757 (doi: 10.1109/TVLSI.2009.2025952).
-
11)
-
1. National Institute of Standards and Technology (NIST): ‘Advanced encryption standard (AES)’ (FIPS Publication 197, 2001).
-
12)
-
10. Dong, L., Wu, N., Zhang, X.: ‘Low power state machine design for AES encryption coprocessor’. Int. Multi-Conf. Engineers and Computer Scientists, Hong Kong, March 2015, pp. 714–717.
-
13)
-
5. Jarvinen, T., Salmela, P., Hamalainen, P., et al: ‘Efficient byte permutation realizations for compact AES implementations’. 13th European Signal Processing Conf., Antalya, Turkey, September 2005, pp. 1–4.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.2151
Related content
content/journals/10.1049/el.2017.2151
pub_keyword,iet_inspecKeyword,pub_concept
6
6