access icon free Optimised CORDIC-based atan2 computation for FPGA implementations

© The Institution of Engineering and Technology
Received 01/06/2017, Published 21/08/2017

A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture.

Inspec keywords: digital arithmetic; field programmable gate arrays; table lookup

Other keywords: coordinate rotation digital computer algorithm; z-path computation; optimised CORDIC-based atan2 computation; look-up table-based FPGA resources; atan2 operator

Subjects: Logic circuits; Digital arithmetic methods; Logic and switching circuits

References

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    2. 2)
      • 2. de Dinechin, F., Istoan, M.: ‘Hardware implementations of fixed-point atan2’. 22nd Symp. Computer Arithmetic, Lyon, France, June 2015, pp. 34–40, doi: 10.1109/ARITH.2015.23.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.2090
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