access icon free 3.8 mW 10 Gbit/s CDR for intra-panel interface with a modulated training pattern

A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electro-magnetic interference characteristics can be improved over the conventional training pattern. A phase-locked loop-based CDR circuit with the proposed scheme in a 65 nm CMOS technology is designed. The measured lock range was between 6 and 10 Gbit/s and the power efficiency was 0.38 mW/Gbit/s at 10 Gbit/s inputs.

Inspec keywords: CMOS integrated circuits; clock and data recovery circuits; phase locked loops; electromagnetic interference; integrated circuit design

Other keywords: bit rate 10 Gbit/s; multiphase clock generation; bit rate 6 Gbit/s; CMOS technology; rising edge position; phase-locked loop-based CDR circuit; power-efficient clock and data recovery circuit design; display data; size 65 nm; modulated training pattern; power 3.8 mW; delay cells; intra-panel interface; electromagnetic interference characteristics

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits; Modulators, demodulators, discriminators and mixers

References

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      • 2. Jang, S.C., Song, H.S., Ye, S., et al: ‘A 13.8 mW 3.0 Gb/s clock-embedded video interface with DLL-based data-recovery circuit’. ISSCC Digest of Technical Papers, San Francisco, CA, USA, February 2011, pp. 450452.
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      • 4. Kwon, J.-W., Park, S.M., Yoo, H.: ‘A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface’. Proc. ESSCIRC, Bordeaux, France, September 2012, pp. 454457.
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      • 3. Baek, D.H., Kim, B., Park, H., et al: ‘A 5.67 mW 9 Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface’. ISSCC Digest of Technical Papers, San Francisco, CA, USA, February 2014, pp. 4850.
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      • 1. Yamguchi, K., Yoshihiko, H., Nakajima, K., et al: ‘A 2.0 Gb/s clock-embedded interface for full-HD 10b 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery’. ISSCC Digest of Technical Papers, San Francisco, CA, USA, February 2009, pp. 192194.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.1726
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