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1887

access icon free Power-efficient flash ADC with complementary voltage-to-time converter

© The Institution of Engineering and Technology
Received 06/04/2017, Published 12/05/2017

A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC.

Inspec keywords: power convertors; CMOS logic circuits; analogue-digital conversion; integrated circuit design

Other keywords: CVTC; power-efficient complementary voltage-to-time converter; CMOS process; signal development direction; power-efficient flash ADC; alternating reset direction; word length 5 bit; logic circuit; power consumption; size 40 nm

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; A/D and D/A convertors; Logic and switching circuits; Logic circuits; Power electronics, supply and supervisory circuits; A/D and D/A convertors; CMOS integrated circuits

References

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      • 1. Oh, D.-R., Kim, J.-I., Seo, M.-J., Kim, J.-G., Ryu, S.-T.: ‘A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS’. IEEE ESSCIRC, Graz, Austria, September 2015, pp. 323–326, doi: 10.1109/ESSCIRC.2015.7313892.
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      • 3. Zhu, S., Xu, B., Wu, B., Soppimath, K., Chiu, Y.: ‘A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM’. IEEE CICC, San Jose, CA, USA, September 2015, pp. 1–4, doi: 10.1109/CICC.2015.7338384.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.1287
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