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access icon free Statistical estimator for simultaneous noise and mismatch suppression in SAR ADC

  • Author(s): I. Banerjee 1  and  A. Sanyal 2
    • View affiliations
    • Affiliations: 1: Department of Radiology, Stanford University, Stanford, CA, USA ;
      2: Department of Electrical Engineering, The State University of New York at Buffalo, Buffalo, NY, USA
  • Source: Volume 53, Issue 12, 08 June 2017, p. 773 – 775
    DOI:  10.1049/el.2017.0928 , Print ISSN 0013-5194, Online ISSN 1350-911X
© The Institution of Engineering and Technology
Received 15/03/2017, Published 03/05/2017

A statistical estimator based on maximum-likelihood estimation theory is developed to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR ADC). After the SAR ADC has finished quantisation, the residue voltage is available at the comparator input and is estimated accurately by using the statistical estimator. The ADC resolution is improved by subtracting the estimated residue from the digital output. The same technique of residue extraction is used to estimate mismatches in the capacitive digital-to-analogue converter. A 7 dB improvement is shown in signal-to-noise-plus-distortion ratio by using the statistical estimator for an 11-bit SAR over a wide range of capacitance mismatch and ADC noise.

Inspec keywords: capacitors; integrated circuit noise; maximum likelihood estimation; comparators (circuits); digital-analogue conversion; quantisation (signal)

Other keywords: signal-to-noise-plus-distortion ratio; quantisation; noise suppression; statistical estimator; mismatch suppression; residue extraction; capacitor mismatch reduction; comparator; capacitive digital-to-analogue converter; SAR ADC; word length 11 bit; maximum-likelihood estimation theory; successive approximation register analogue-to-digital converter

Subjects: A/D and D/A convertors; Other topics in statistics; Capacitors; A/D and D/A convertors; Other digital circuits; Other topics in statistics

References

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      • 8. Chen, L., Ma, J., Sun, N.: ‘Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection’, IEEE Int. Symp. on Circuits and Systems (ISCAS), Melbourne, Australia, June 2014, pp. 2357–2360.
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      • 4. Chen, L., Tang, X., Sanyal, A., Yoon, Y., Cong, J., Sun, N.: ‘A 10.5-b ENOB 645nW 100kS/s SAR ADC with statistical estimation based noise reduction’. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, September 2015, pp. 1–4.
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      • 1. Sanyal, A., Sun, N.: ‘A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration’. IEEE Sym. Very-Large Scale Integrated Circuits, Honolulu, HI, USA, June 2016, pp. 26–27.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.0928
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