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1887

access icon free Time-shifted excess loop delay compensation DAC for 2-T s delay in CT-ΔΣ ADCs

This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but ignored in the conventional methods, and therefore no additional hardware is required. Simulation results and mathematical analysis are provided to verify the effectiveness of the proposed structure.

References

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      • 1. Dong, Y., Zhao, J., Yang, W., et al: ‘A 930 mW 69 dB-DR 465 MHz-BW CT 1-2 MASH ADC in 28 nm CMOS’. ISSCC Dig. Tech. Papers, San Francisco, CA, USA, February 2016, pp. 279280.
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      • 2. Wu, S.-H., Kao, T.-K., Lee, Z.-M., Chen, P., Tsai, J.-Y.: ‘A 160 MHz-BW 72 dB-DR 40 mW continuous-time ΔΣ modulator in 16 nm CMOS with analog ISI-reduction technique’. ISSCC Dig. Tech. Papers, San Francisco, CA, USA, February 2016, pp. 280282.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.0628
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content/journals/10.1049/el.2017.0628
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