access icon free Process enabling highly accurate die position for fan-out package applications

A new process that can improve die shift issue in process utilising back-sided under bump metallurgy (UBM) via a self-alignment effect for fan-out package applications is proposed. The die and the pad of the substrate are spontaneously aligned and the degree of accuracy is very high after reflow. For the experiment, two kinds of UBM pads were prepared on glass dies and the SAC305 solder was formed on the copper pads of an frame retardent (FR)-based substrate. The die shift value was from 20 to 50 μm after pick-and-placement. After reflow, the maximum die shift value was <1 μm. An initially misaligned die with a large shift was aligned with a high degree of accuracy during reflow due to the surface tension of the molten solder. The proposed process improves the die shift issue in the fabrication of fan-out wafer-level packaging and the active die embedded substrate.

Inspec keywords: position control; wafer level packaging

Other keywords: fan out wafer level packaging; SAC305 solder; die shift issue; die shift value; glass dies; process enabling highly accurate die position; back-sided under bump metallurgy; self-alignment effect; FR-4-based substrate; active die embedded substrate; fan-out package applications; UBM pads; copper pads

Subjects: Semiconductor integrated circuits; Product packaging

References

    1. 1)
      • 3. Che, F.X., Ho, D., Ding, J.P., et al: ‘Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging technology’. Proc. IEEE 17th Electronics Packaging Technology Conf., Singapore, December 2015, pp. 18.
    2. 2)
      • 6. Khong, C.H., Kumar, A., Zhang, X., et al: ‘A novel method to predict die shift during compression molding in embedded wafer level package’. Proc. IEEE Electronic Components Technology Conf., San Diego, CA, USA, May 2009, pp. 535541.
    3. 3)
      • 7. Liu, F., Kubo, A., Nair, C., et al: ‘Next generation panel-scale RDL with ultra small photo vias and ultra-fine embedded trenches for low cost 2.5D interposers and high density fan-out WLP’’. Proc. IEEE Electronic Components Technology Conf., Las Vegas, NV, USA, May–June 2016, pp. 11571522.
    4. 4)
      • 5. Mazuir, J., Olmeta, V., Yin, M., et al: ‘Evaluation and optimization of die-shift in embedded wafer-level packaging by enhancing the adhesion strength of silicon chips to carrier wafer’. Proc. IEEE 13th Electronics Packaging Technology Conf., Singapore, December 2011, pp. 747751.
    5. 5)
      • 4. Eric Kuah, T.H., Hao, J.P., Yin, M., et al: ‘Encapsulation challenges for wafer level packaging’. Proc. IEEE Microelectronics and Packaging Conf., Singapore, December 2009.
    6. 6)
      • 8. Humpston, G., Jacobson, D.M.: ‘Principles of soldering’ (ASM International, The Materials Information Society, Materials Park, OH, USA, 2004).
    7. 7)
      • 1. Liu, P., Wang, J., Tong, L., et al: ‘Advances in the fabrication process and applications of wafer level packaging’, J. Electron. Packag., 2014, 136, pp. 17.
    8. 8)
      • 2. Tseng, C.-F., Liu, C.-S., Wu, C.-H., et al: ‘In FO (wafer level integrated fan-out) technology’. Proc. IEEE 66th Electronic Components and Technology Conf., Las Vegas, NV, USA, May–June 2016, pp. 16.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2017.0357
Loading

Related content

content/journals/10.1049/el.2017.0357
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Correspondence
This article has following corresponding article(s):
in brief