© The Institution of Engineering and Technology
An unreliability-based information bit flipping (UIBF) decoding using cyclic redundancy check is proposed to lower the error floors of high-rate systematic low-density parity-check (LDPC) codes. Unsuccessfully decoded codeword is redecoded by the UIBF decoding with very low complexity at the end of every iteration of the sum–product (SP) decoding. The proposed scheme is applied to LDPC codes of the IEEE 802.16e standard. Simulation results show that the proposed scheme effectively lowers the error floors of systematic LDPC codes with smaller number of iterations compared with the conventional SP decoding scheme, which leads to the reduced power consumption and increased data throughput.
References
-
-
1)
-
7. Han, Y., Ryan, W.E.: ‘Low-floor decoders for LDPC codes’, IEEE Trans. Commun., 2009, 57, (6), pp. 1663–1673 (doi: 10.1109/TCOMM.2009.06.070325).
-
2)
-
10. Kang, J., Huang, Q., Lin, S., Abdel-Ghaffar, K.: ‘An iterative decoding algorithm with backtracking to lower the error-floors of LDPC codes’, IEEE Trans. Commun., 2011, 59, (1), pp. 64–73 (doi: 10.1109/TCOMM.2010.101210.090628).
-
3)
-
9. Zhang, X., Chen, S.: ‘A two-stage decoding algorithm to lower the error-floors for LDPC codes’, IEEE Commun. Lett., 2015, 19, (4), pp. 517–520 (doi: 10.1109/LCOMM.2015.2401554).
-
4)
-
8. Shin, B., Park, H., No, J.-S., Chung, H.: ‘Multi-stage decoding scheme with post-processing for LDPC codes to lower the error floors’, IEICE Trans. Commun., 2011, E94-B, (8), pp. 2375–2377 (doi: 10.1587/transcom.E94.B.2375).
-
5)
-
2. Zhao, K., Li, J., Ma, J., Micheloni, R., Zhang, T.: ‘Overclocking NAND flash memory I/O link in LDPC-based SSDs’, IEEE Trans. Circuits Syst. II, Express Briefs, 2014, 61, (11), pp. 885–889 (doi: 10.1109/TCSII.2014.2350377).
-
6)
-
6. Richardson, T.: ‘Error floors of LDPC codes’. Proc. of 41st Allerton Conf. on Communication, Control, and Computing, Monticello, IL, USA, October 2003, pp. 1426–1435.
-
7)
-
13. MacKay, D.J.C.: ‘Good error correcting codes based on very sparse matrices’, IEEE Trans. Inf. Theory, 1999, 45, (2), pp. 399–431 (doi: 10.1109/18.748992).
-
8)
-
11. Zhang, Z., Dolecek, L., Nikolic, B., Anantharam, V., Wainwright, M.: ‘GEN03-6: investigation of error floors of structured low-density parity-check codes by hardware emulation’. Proc. of 49th IEEE Global Telecommunications Conf., San Francisco, CA, USA, November 2006, pp. 1–6.
-
9)
-
5. Ajaz, S., Lee, H.: ‘Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for Gbit wireless communication’, Electron. Lett., 2013, 49, (19), pp. 1246–1248 (doi: 10.1049/el.2013.1673).
-
10)
-
3. Zhang, Y., Zhang, C., Yan, Z., Chen, S., Jiang, H.: ‘A high-throughput multi-rate LDPC decoder for error correction of solid-state drives’. Proc. of IEEE Workshop on Signal Processing Systems (SiPS), Hangzhou, China, October 2015, pp. 1–6.
-
11)
-
4. .: ‘IEEE standard for local and metropolitan area network part 16: air interface for fixed and mobile broadband access systems’, 2004.
-
12)
-
12. Kodali, R.K., Boppana, L.: ‘FPGA implementation of energy efficient multiplication over GF(2m) for ECC’. Proc. of Int. Conf. on Advances in Computing, Communications and Informatics, Delhi, India, September 2014, pp. 1815–1821.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.2827
Related content
content/journals/10.1049/el.2016.2827
pub_keyword,iet_inspecKeyword,pub_concept
6
6