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access icon free 2.5 mW 2.73 GHz non-overlapping multi-phase clock generator with duty-cycle correction in 0.13 µm CMOS

A high-speed low power multi-phase clock generator with a simple duty-cycle correction circuit is presented. By adding tail transistors driven by the out-phase signal as a discharge path to correct the phase overlapping in the conventional design, 25% duty cycle multi-phase clocks are obtained with <1° phase error. Thanks to this simple topology, the proposed work is featured with fast-speed, low power with a small silicon area. Fabricated in a 0.13 µm RF CMOS process, the proposed clock generator has a measured operating frequency up to 2.73 GHz with a maximum power consumption of 2.5 mW from a 1.2 V supply.

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.1232
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content/journals/10.1049/el.2016.1232
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