RT Journal Article
A1 G. Giustolisi
AD DIEEI, Università di Catania, Catania, Italy
A1 G. Palumbo
AD DIEEI, Università di Catania, Catania, Italy

PB iet
T1 Compensation strategy for high-speed three-stage switched-capacitor amplifiers
JN Electronics Letters
VO 52
IS 14
SP 1202
OP 1204
AB In this Letter a new compensation strategy for a class of three-stage operational transconductance amplifiers is proposed. The proposed approach reduces the original third-order transfer function of the loop gain to that of a pure two-pole amplifier thus allowing the designer to use well-known and consolidated design rules. The approach, suitable for high-speed switched-capacitor circuits, is validated by means of intensive Monte Carlo simulations on a 65-nm three-stage CMOS amplifier.
K1 compensation strategy
K1 three-stage operational transconductance amplifiers
K1 loop gain
K1 third-order transfer function
K1 three-stage CMOS amplifier
K1 high-speed three-stage switched-capacitor amplifiers
K1 Monte Carlo simulations
K1 size 65 nm
DO https://doi.org/10.1049/el.2016.1210
UL https://digital-library.theiet.org/;jsessionid=1nj0lgj4x5eqj.x-iet-live-01content/journals/10.1049/el.2016.1210
LA English
SN 0013-5194
YR 2016
OL EN