access icon free Comparator offset calibration using unbalanced clocks for high speed and high power efficiency

A novel comparator offset calibration using unbalanced clocks is proposed. The new technique avoids loading the comparator core with trimming elements, thus maximising the comparator speed and power efficiency. Simulations show that a comparator utilising the proposed calibration achieves near-native speed and noise performance. It also achieves superior energy-delay-noise product over comparators with conventional calibrations.

Inspec keywords: clocks; calibration; comparators (circuits)

Other keywords: high-power efficiency; energy-delay-noise product; comparator offset calibration; unbalanced clocks; high speed comparator; trimming elements

Subjects: Other digital circuits; Measurement standards and calibration

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.1157
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content/journals/10.1049/el.2016.1157
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