RT Journal Article
A1 Shiuh-hua Wood Chiang
AD Electrical and Computer Engineering Department, Brigham Young University, Provo, UT 84602, USA

PB iet
T1 Comparator offset calibration using unbalanced clocks for high speed and high power efficiency
JN Electronics Letters
VO 52
IS 14
SP 1206
OP 1207
AB A novel comparator offset calibration using unbalanced clocks is proposed. The new technique avoids loading the comparator core with trimming elements, thus maximising the comparator speed and power efficiency. Simulations show that a comparator utilising the proposed calibration achieves near-native speed and noise performance. It also achieves superior energy-delay-noise product over comparators with conventional calibrations.
K1 high-power efficiency
K1 energy-delay-noise product
K1 comparator offset calibration
K1 unbalanced clocks
K1 high speed comparator
K1 trimming elements
DO https://doi.org/10.1049/el.2016.1157
UL https://digital-library.theiet.org/;jsessionid=an370qmc7nfa.x-iet-live-01content/journals/10.1049/el.2016.1157
LA English
SN 0013-5194
YR 2016
OL EN