@ARTICLE{ iet:/content/journals/10.1049/el.2016.1036, author = {Zhao Zhang}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, author = {Jincheng Yang}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, author = {Liyuan Liu}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, author = {Peng Feng}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, author = {Jian Liu}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, author = {Nanjian Wu}, affiliation = { State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People's Republic of China }, keywords = {reverse leakage compensation technique;SSCP;CMOS switches;source-switched charge pump;source-drain voltage;frequency 0.7 GHz to 1.6 GHz;reverse sub-threshold leakage;size 65 nm;wideband PLL;inverters;current-source N-type MOS-P-type MOS;spur level reduction;NMOS capacitor;}, ISSN = {0013-5194}, language = {English}, abstract = {A source-switched charge pump (SSCP) with reverse leakage compensation technique is proposed to reduce spur level of wideband PLL induced by the reverse sub-threshold leakage of the charge pump. This technique can set the source–drain voltage of current-source N-type MOS (NMOS)/P-type MOS to be close to zero at off-state of the charge pump and thus reduce the reverse leakage. Compared with the conventional SSCP, only one NMOS capacitor, two CMOS switches and two inverters are added in the proposed charge pump. So, there is negligible extra power and extra area cost. A 0.7–1.6 GHz PLL is designed with the conventional and the proposed charge pumps in 65 nm CMOS process. Simulation results show the proposed SSCP can reduce orders of the magnitude of the reverse leakage without the penalty of current matching, compared with the conventional charge pump. The PLL with the proposed charge pump achieves up to 28 dB spur level reduction.}, title = {Source-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL}, journal = {Electronics Letters}, issue = {14}, volume = {52}, year = {2016}, month = {July}, pages = {1211-1212(1)}, publisher ={Institution of Engineering and Technology}, copyright = {© The Institution of Engineering and Technology}, url = {https://digital-library.theiet.org/;jsessionid=1l72g02vi9jh3.x-iet-live-01content/journals/10.1049/el.2016.1036} }