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Improved self-blocking flip-flop design

Improved self-blocking flip-flop design

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An improved self-blocking flip-flop design is proposed. With smaller clock load and simpler structure, the proposed design is compared with previous flip-flop structures. In the same size of input/output transistors and load capacitance, the proposed structure shows a better performance in speed improvement and power saving by simulation.

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.0836
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