access icon free Low-power technique for dynamic comparators

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.

Inspec keywords: power consumption; comparators (circuits); preamplifiers; low-power electronics

Other keywords: power consumption reduction; low-power technique; dynamic comparators; comparator pre-amplification phase

Subjects: Other digital circuits; Amplifiers

References

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      • 7. Abbas, M., Furukawa, Y., Komatsu, S., Takahiro, J., Asada, K.: ‘Clocked comparator for high-speed applications in 65 nm technology’. 2010 IEEE Asian Solid State Circuits Conf. (A-SSCC), November 2010, pp. 14.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.3805
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