Implementation of low-power, non-volatile latch utilising ferroelectric transistor
The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.
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