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Implementation of low-power, non-volatile latch utilising ferroelectric transistor

Implementation of low-power, non-volatile latch utilising ferroelectric transistor

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The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.

References

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      • J. Evans . (2011)
        1. Evans, J.: ‘Modeling radiant thin ferroelectric film transistors’ (Radiant Technologies, Inc., Albuquerque, NM, USA, 2011).
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      • S. Yamamoto , S. Inoue , H. Ishiwara .
        3. Yamamoto, S., Inoue, S., Ishiwara, H.: ‘Analysis of non-volatile latch circuits with ferroelectric-gate field effect transistors for low power and low voltage operation’. 23rd Int. Conf. Microelectronics, Nis, Yugoslavia, May2002, pp. 589592.
        . 23rd Int. Conf. Microelectronics, Nis, Yugoslavia, May , 589 - 592
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      • S.T. Philpy , D.A. Kamp , G.F. Derbenwick .
        4. Philpy, S.T., Kamp, D.A., Derbenwick, G.F.: ‘Nonvolatile and SDRAM ferroelectric memories for aerospace applications’. Proc. of 2004 IEEE Aerospace Conf., Big Sky, MT, USA, March 2004, pp. 22942299.
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