Nanoscale CMOS battery cells for gate level on-chip security designs
An efficient power analysis attack countermeasure at the transistor gate level using novel nanoscale CMOS battery cells in a decoupling-based technique is presented. The proposed CMOS battery cells are used as decoupling elements between the gates implementing a sensitive operation inside a cryptographic module and the power supply rail of the integrated circuit. As a result, the battery cells form an intermediate on-chip power storage element, providing a masked power supply point for gates that are on a critical security path. The circuitry of the battery cells and the gates are designed using 65 nm TSMC CMOS technology. A test system was simulated with an 8 bit XOR serving as a target operation for a correlation power analysis attack. A total of 16 battery cells, two per gate for complementary cycles, were created with 1.74 µm2 P-type MOS transistors serving as energy storage devices. Results showed that the test system offered protection at 10 000 traces.
