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access icon free Area-efficient video transform for HEVC applications

A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.

References

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      • 6. Chiang, P.T., Chang, T.S.: ‘A reconfigurable inverse transform architecture design for HEVC decoder’. Proc. of IEEE Int. Symp. on Circuits and Systems, Beijing, China, May 2013, pp. 10061009.
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      • 4. Shen, S., Shen, W., Fan, Y., Zeng, X.: ‘A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards’. Proc. of IEEE Int. Conf. Multimedia Expo, San Jose, CA, USA, July 2012, pp. 788793.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.1085
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