access icon free 4×, 3-level, blind ADC-based receiver

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <10 12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UIpp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.

Inspec keywords: CMOS digital integrated circuits; clock and data recovery circuits; receivers; decision feedback equalisers; analogue-digital conversion

Other keywords: FR4 channel; CDR design; power 63 mW; 4× 3-level blind ADC-based receiver; bit rate 5 Gbit/s; power consumption; speculative decision-feedback equaliser; size 65 nm; digital clock and data recovery design; DFE; bit error rate; BER; power 86 mW; analogue-to-digital converter; high-frequency jitter tolerance; CMOS technology

Subjects: Other analogue circuits; A/D and D/A convertors; CMOS integrated circuits; A/D and D/A convertors

References

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.4441
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