access icon free Column-level passive sample and column-shared active readout structure for high speed, low power ROIC

© The Institution of Engineering and Technology
Received 23/09/2014, Published 19/02/2015

A novel odd–even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is <55 mW when operating at 200 Hz frame rate with four outputs and the linearity is 99.95%.

Inspec keywords: low-power electronics; CMOS integrated circuits; infrared detectors; integrated circuit design; operational amplifiers; indium compounds; readout electronics

Other keywords: medium-scale array design; size 0.35 mum; CMOS process; CTIA; power consumption; column-level passive sample structure; low power ROIC; high speed low noise readout IC; cooled infrared detector; column capacitive transimpedance amplifier; InSb; column-shared active readout structure

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits; Photodetectors; Power electronics, supply and supervisory circuits; Amplifiers

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