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access icon free 2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 µm CMOS technology

© The Institution of Engineering and Technology
Received 13/03/2014, Published 27/05/2014

A 2 GHz sub-harmonically injection-locked phase-locked loop (SILPLL) with a self-aligned injection window is presented. The SILPLL adopts a mixer-based self-align technique to automatically adjust the injection timing, overcoming the speed limitation of the phase detection. Circuit techniques such as a symmetrical mixer and a V/I converter with mismatch cancellation are adopted to improve injection timing accuracy. Fabricated in a 180 nm CMOS technology, the SILPLL exhibits −127 dBc/Hz phase noise at 1 MHz offset and draws 6.9 mA current from a 1.8 V power supply. The measured root-mean-square jitter integrating from 1 kHz to 40 MHz is 214 fs and the reference spur is −61 dBc.

Inspec keywords: phase detectors; integrated circuit technology; phase locked loops; integrated circuit manufacture; integrated circuit noise; CMOS integrated circuits; phase convertors; phase noise; UHF integrated circuits; UHF mixers

Other keywords: mixer-based injection timing control; SILPLL; self-aligned injection window; mixer-based self-align technique; voltage 1.8 V; mismatch cancellation; CMOS technology; current 6.9 mA; root-mean-square jitter; V-I converter; symmetrical mixer; time 214 fs; subharmonically injection-locked phase-locked loop; phase noise; phase detection; size 0.18 mum; frequency 2 GHz; frequency 1 kHz to 40 MHz

Subjects: CMOS integrated circuits; Modulators, demodulators, discriminators and mixers; Convertors; Microwave integrated circuits

References

    1. 1)
      • 5. Helal, B.M., et al: ‘A low jitter programmable clock multiplier base on a pulse injection locked oscillator with a highly digital tuning loop’. IEEE JSSC, 2009, 44, (5), pp. 1391–1400.
    2. 2)
      • 4. Gao, X., et al: ‘A 2.2 GHz 7.6 mW sub-sampling PLL with −126 dBc/Hz in-band phase noise and 0.15 ps rms jitter in 0.18 μm CMOS’. ISSCC, San Francisco, CA, USA, February 2009.
    3. 3)
      • 1. Liang, C.-F., et al: ‘An injection-locked ring PLL with self-aligned injection window’. ISSCC, San Francisco, CA, USA, February 2011.
    4. 4)
      • 3. Le, I.-T., et al: ‘A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing’. ISSCC, San Francisco, CA, USA, February 2013.
    5. 5)
      • 2. Huang, Y.-C., et al: ‘A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing’. ISSCC, San Francisco, CA, USA, February 2012.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.0825
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