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Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process

Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process

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An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.

References

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      • 2. Lofstrom, K., Daasch, W.R., Taylor, D.: ‘IC identification circuit using device mismatch’. Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, February 2000, pp. 372373.
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      • 3. Su, Y., Holleman, J., Otis, B.: ‘A 1.6 pJ/bit 96% stable chip-ID generating circuit using process variations’. Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, February 2007, pp. 406408.
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      • 4. Stanzione, S., Iannaccone, G.: ‘Silicon physical unclonable function resistant to a 1025-trial brute force attack in 90 nm CMOS’. Proc. IEEE Symp. on VLSI Circuits, Kyoto, Japan, June 2009, pp. 116117.
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