Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Low-power high-speed full adder for portable electronic applications

  • Author(s): C.-K. Tung 1 ; S.-H. Shieh 2 ; C.-H. Cheng 3
    • View affiliations
    • Affiliations: 1: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, Taichung, Taiwan;
      2: Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung, Taiwan;
      3: Department of Electronic Engineering, Feng Chia University, Taichung, Taiwan
  • Source: Volume 49, Issue 17, 15 August 2013, p. 1063 – 1064
    DOI:  10.1049/el.2013.0893 , Print ISSN 0013-5194, Online ISSN 1350-911X
© The Institution of Engineering and Technology
Received 16/04/2013, Published

A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60–73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to provide a 20.4–21.2% power saving, a 12.3–67.0% delay time reduction and a 35–102% reduction in power delay product compared with the referenced FAs. In short, an LPHS-FA is presented in a concise form as a high-performance FA in practical applications.

Inspec keywords: CMOS digital integrated circuits; low-power electronics; MOSFET; adders

Other keywords: HSPICE simulations; low-power high-speed full adder; metal oxide semiconductor field effect transistors; size 0.18 mum; power delay product; LPHS-FA; delay time reduction; portable electronic applications; circuit complexity reduction; MOSFET; TSMC CMOS process technology

Subjects: Logic circuits; Insulated gate field effect transistors; Logic and switching circuits; CMOS integrated circuits

References

    1. 1)
      • 1. Bui, H.T., Wang, Y., Jiang, Y.: ‘Design and analysis of low-power 10-transistor full adders using novel XOR–XNOR gates’, IEEE Trans. Circuits Syst. II, 2002, 49, (1), pp. 25–30 (doi: 10.1109/82.996055).
    2. 2)
      • 2. Lin, J.-F., Hwang, Y.-T., Sheu, M.-H., Ho, C.-C.: ‘A novel high-speed and energy efficient 10-transistor full adder design’, IEEE Trans. Circuits Syst. I, 2007, 54, (5), pp. 1050–1059 (doi: 10.1109/TCSI.2007.895509).
    3. 3)
      • 3. Radhakrishnan, D.: ‘Low-voltage low-power CMOS full adder’, IEE Proc., Circuits Devices Syst., 2001, 148, (1), pp. 19–24 (doi: 10.1049/ip-cds:20010170).
    4. 4)
      • 6. Aguirre-Hernandez, M., Linares-Aranda, M.: ‘CMOS full-adders for energy-efficient arithmetic applications’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2011, 19, (4), pp. 718–721 (doi: 10.1109/TVLSI.2009.2038166).
    5. 5)
      • 4. Chang, C.-H., Gu, J., Zhang, M.: ‘A review of 0.18-um full adder performances for tree structured arithmetic circuits’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2005, 13, (6), pp. 686–695 (doi: 10.1109/TVLSI.2005.848806).
    6. 6)
      • 5. Goel, S., Kumar, A., Bayoumi, M.A.: ‘Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2006, 14, (12), pp. 1309–1321 (doi: 10.1109/TVLSI.2006.887807).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2013.0893
Loading

Related content

content/journals/10.1049/el.2013.0893
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address