access icon free High performance floating-gate technology compatible antifuse

An antifuse structure that is fully compatible with the standard floating-gate technology is presented. The antifuse consists of an oxide-nitride-oxide dielectric layer, sandwiched between polysilicon and N-well layers. The characteristics of the antifuse are investigated. The off-state resistance of the antifuse is larger than 10 GΩ. The programmed antifuses show linear ohmic characteristics and have a tight resistance distribution centred around 350 Ω. The time dependent dielectric breakdown measurements show that the extrapolated lifetime of the unprogrammed antifuse at 5.5 V is as long as 40 years, and the resistance change of post-program antifuses under the continuous reading mode test is lower than 5%.

Inspec keywords: integrated memory circuits; dielectric materials; semiconductor-insulator boundaries; field programmable gate arrays; elemental semiconductors; silicon

Other keywords: TDDB measurements; N-well layers; off-state resistance; floating-gate technology; voltage 5.5 V; antifuse structure; dielectric layer; polysilicon

Subjects: Memory circuits; Logic circuits; Other semiconductor interfaces and junctions; Semiconductor storage; Dielectric materials and properties; Logic and switching circuits

References

    1. 1)
      • 7. Cha, H.K.: ‘A 32-KB standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller’, IEEE J. Solid-State Circuits,2006, 41, (9), pp. 21152124 (doi: 10.1109/JSSC.2006.880603).
    2. 2)
      • 3. Wee, J.K., Yang, W., Ryou, E.-K., Choi, J.-S., Ahn, S.-H., Chung, J.-Y., Kim, S.-C.: ‘An antifuse EPROM circuitry scheme for field-programmable repair in DRAM’, J. Solid-State Circuits, 2000, 35, (10), pp. 14081414 (doi: 10.1109/4.871316).
    3. 3)
      • 2. Harndy, E.: ‘Dielectric based antifuse for logic and memory ICs’, Tech. Dig. IEDM, San Francisco, CA, USA, December 1988, pp. 786789.
    4. 4)
      • 1. Greene, J., Harndy, E., Beal, S.: ‘Antifuse field programmable gate arrays’, Proc. IEEE, 1993, 81, (7), pp. 10421056 (doi: 10.1109/5.231343).
    5. 5)
      • 5. Chiang, S.: ‘Oxide-nitride-oxide antifuse reliability’. IEEE Int. Reliability Physics Symp., New Orleans, LA, USA, 1990, pp. 186192.
    6. 6)
      • 6. Kim, J., Lee, K.: ‘3-transistor cell OTP ROM array using standard CMOS gate-oxide antifuses’, J. Semicond. Technol. Sci., 2003, 3, (4), pp. 205210.
    7. 7)
      • 4. Zhang, G.: ‘Reliable metal-to-metal oxide antifuses’. Proc. IEDM, San Francisco, CA, USA, December 1994, pp. 281284.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2012.3574
Loading

Related content

content/journals/10.1049/el.2012.3574
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Correspondence
This article has following corresponding article(s):
in brief