10 Gbit/s bit interleaving CDR for low-power PON

10 Gbit/s bit interleaving CDR for low-power PON

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A novel, low power, downstream clock and data recovery (CDR)-decimator architecture is proposed for next generation, energy efficient 10 Gbit/s optical network units (ONUs). The architecture employs a new time division multiplexing bit-interleaving downstream concept for passive optical networks (Bi-PON) allowing early decimation of the incoming data and lowering of the processing speed to the user rate of the ONU, thus reducing the power consumption significantly.


    1. 1)
      • ITU-T G. Sup45: GPON power conservation, 2009.
    2. 2)
      • Suzuki, N., Kobiki, K., Igawa, E., Nakagawa, J.: `Dynamic sleep-mode ONU with self-sustained fast-lock CDR for power saving in 10G-EPON systems', ECOC 2011, Geneva, Switzerland, We.8.C.4.
    3. 3)
      • Kanonakis, K., Zhang, J., Cvijetic, N., Tomkos, I., Wang, T.: `1G/10G-EPON compliant scheme combining ONU energy efficiency with QoS performance', OFC'12, Los Angles, CA, USA, JTh2A.52.
    4. 4)
      • IEEE P802.3az Energy Efficient Ethernet Task Force.
    5. 5)
    6. 6)
      • Chow, H., Suvakovic, D., van Veen, D., Dupas, A., Boislaigue, R., Farah, R., Fai Lau, M., Galaro, J., Qua, G., Anthapadmanabhan, N.P., Torfs, G., Van Praet, C., Yin, X., Vetter, P.: `Demonstration of low-power bit-interleaving TDM PON', ECOC, 2012, Amsterdam, The Netherlands, Mo.2.B.1.

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