10 Gbit/s bit interleaving CDR for low-power PON
A novel, low power, downstream clock and data recovery (CDR)-decimator architecture is proposed for next generation, energy efficient 10 Gbit/s optical network units (ONUs). The architecture employs a new time division multiplexing bit-interleaving downstream concept for passive optical networks (Bi-PON) allowing early decimation of the incoming data and lowering of the processing speed to the user rate of the ONU, thus reducing the power consumption significantly.
- ITU-T G. Sup45: GPON power conservation, 2009.
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- IEEE P802.3az Energy Efficient Ethernet Task Force.
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- Chow, H., Suvakovic, D., van Veen, D., Dupas, A., Boislaigue, R., Farah, R., Fai Lau, M., Galaro, J., Qua, G., Anthapadmanabhan, N.P., Torfs, G., Van Praet, C., Yin, X., Vetter, P.: `Demonstration of low-power bit-interleaving TDM PON', ECOC, 2012, Amsterdam, The Netherlands, Mo.2.B.1.