Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free All-digital PLL with ΔΣ DLL embedded TDC

© The Institution of Engineering and Technology
Received 29/08/2012, Published

An all-digital PLL (ADPLL) which employs a ΔΣ delay-locked loop (DLL) to achieve a PVT-insensitive time resolution of the time-to-digital converter (TDC) as well as noise-shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in-band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the ΔΣ DLL consumes 2.1 mW.

Inspec keywords: phase locked loops; CMOS integrated circuits; time-digital conversion; delay lock loops

Other keywords: all-digital PLL; in-band phase noise; ΔΣ DLL embedded TDC; noise-shaped dithering; ΔΣ delay-locked loop; CMOS; size 65 nm; time-to-digital converter; frequency 1.8 GHz; power 14.3 mW; power 2.1 mW

Subjects: CMOS integrated circuits; Modulators, demodulators, discriminators and mixers; A/D and D/A convertors

References

    1. 1)
      • 2. Staszewski, R.B., et al: ‘Spur-free all-digital PLL in 65 nm for mobile phones’. Proc. IEEE ISSCC, San Francisco, CA, USA, February 2011, pp. 52–53.
    2. 2)
      • 4. Yu, X., et al: ‘A 0.4–1.6 GHz low-OSR ΔΣ DLL with self-referenced multiphase generation’. Proc. IEEE ISSCC, Grenoble, France, February 2009, pp. 398–399.
    3. 3)
      • 1. Zanuso, M., et al.: ‘Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL’, IEEE Trans. Circuits Syst. I, 2010, 57, pp. 548–555 (doi: 10.1109/TCSI.2009.2023945).
    4. 4)
      • 5. Han, Y., et al: ‘A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL’. Proc. IEEE Symp. on Circuits and Systems., Boise, ID, USA, 2012, pp. 542–545.
    5. 5)
      • 3. Hsu, C.-M., et al: ‘A low-noise, wide-BW 3.6 GHz digital ΔΣ fract.-N frequency synthesizer with a noise-shaping TDC and quantization noise cancellation’. IEEE ISSCC Dig. Tech. Pprs, Grenoble, France, February 2008, pp. 340–341.
    6. 6)
    7. 7)
      • Staszewski, R.B.: `Spur-free all-digital PLL in 65 nm for mobile phones', Proc. IEEE ISSCC, February 2011, San Francisco, CA, USA, p. 52–53.
    8. 8)
      • Hsu, C.-M.: `A low-noise, wide-BW 3.6 GHz digital ΔΣ fract.-N frequency synthesizer with a noise-shaping TDC and quantization noise cancellation', IEEE ISSCC Dig. Tech. Pprs, February 2008, Grenoble, France, p. 340–341.
    9. 9)
      • Han, Y.: `A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL', Proc. IEEE Symp. on Circuits and Systems., 2012, Boise, ID, USA, p. 542–545.
    10. 10)
      • Yu, X.: `A 0.4–1.6 GHz low-OSR ΔΣ DLL with self-referenced multiphase generation', Proc. IEEE ISSCC, February 2009, Grenoble, France, p. 398–399.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2012.3017
Loading

Related content

content/journals/10.1049/el.2012.3017
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address