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SOI LDMOS with variable-k dielectric trench

SOI LDMOS with variable-k dielectric trench

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An SOI LDMOS with a variable-k dielectric trench (VKTLDMOS) is proposed. The low-k dielectric on the top of the trench is used to sustain high voltage and ensure the smallest cell pitch while the high-k dielectric on the bottom of the trench increases the average permittivity of the trench and increases the drift doping. The SiO2 dielectric is in the middle of the high-k and low-k materials. Moreover, the SOI TLDMOS with a different k filling dielectric is also discussed. The high-k dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable for a deep and narrow trench. Simulation shows the VKTLDMOS has the highest FOM BV2/Rs,on compared with that of the conventional SOI TLDMOS.

References

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      • Varadarajan, K.R., Chow, T.P., Wang, J.: `250 V integrable silicon lateral trench power MOSFETs with superior specific on-resistance', Proc. ISPSD, 2007, Jeju, Republic of Korea, p. 233–236.
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      • Zitouni, M., Morancho, F., Rossel, P., Tranduc, H., Buxo, J., Pages, I.: `A new concept for lateral DMOS transistor for smart power IC's', Proc. Int. Symp. on Power Semiconductor Devices and ICs, 1999, Toronto, Canada, p. 73–76.
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