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SPICE-compatible modelling technique for simulating floating-gate transistors

SPICE-compatible modelling technique for simulating floating-gate transistors

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A technique is introduced to enable the simulation of floating-gate transistors within standard analogue circuit simulators, such as SPICE. This technique can be used in all types of circuit simulations, ranging from DC sweeps to charge-modification scenarios. The technique is then used to simulate several analogue circuits, the results of which show strong agreement with identical circuits fabricated in standard CMOS processes.

Inspec keywords: CMOS analogue integrated circuits; MOSFET; circuit simulation; semiconductor device models

Other keywords: charge-modification; SPICE-compatible modelling; circuit simulations; standard CMOS process; floating-gate transistors; standard analogue circuit simulators

Subjects: Analogue circuits; Electronic engineering computing; Semiconductor device modelling, equivalent circuits, design and testing; Computer-aided circuit analysis and design; Insulated gate field effect transistors; CMOS integrated circuits

References

    1. 1)
    2. 2)
      • Yin, L., Embabi, S., Sánchez-Sinencio, E.: `A floating-gate MOSFET D/A converter', Proc. IEEE ISCAS, June 1997, Hong Kong, 1, p. 409–412.
    3. 3)
      • Rahimi, K., Diorio, C., Hernandez, C., Brockhausen, M.: `A simulation model for MOS synapse transistors', Proc. IEEE ISCAS, May 2002, Scottsdale, AZ, USA, 2, p. II-532–II-535.
    4. 4)
      • Mondragon-Torrres, A., Schneider, M., Sánchez-Sinencio, E.: `Extraction of electrical parameters of floating gate devices for circuit analysis, simulation, and design', Proc. IEEE MWSCAS, August 2002, Tulsa, OK, USA, 1, p. I-311–I-314.
    5. 5)
      • Hasler, P., Basu, A., Koziol, S.: `Above threshold pFET injection modeling intended for programming floating-gate systems', Proc. IEEE ISCAS, May 2007, New Orleans, LA, USA, p. 1557–1560.
    6. 6)
      • Gray, J., Robucci, R., Hasler, P.: `The design and simulation model of an analog floating-gate computational element for use in large-scale analog reconfigurable systems', Proc. IEEE MWSCAS, August 2008, Knoxville, TN, USA, 1, p. 253–256.
    7. 7)
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