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Compact quadrature receiver for 24 GHz radar applications in 0.13 µm CMOS

Compact quadrature receiver for 24 GHz radar applications in 0.13 µm CMOS

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A compact low-noise quadrature receiver for 24 GHz ISM applications in 0.13 µm CMOS technology is presented. The chip offers a conversion gain of 18 dB and a noise figure of 5 dB. The differential circuit consumes only 24 mW from a single 1.5 V supply. The low-noise amplifier, two mixers and on-chip quadrature generation are integrated on a minimal chip area of 0.48 mm2 including pads.

References

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      • Cao, Y., Issakov, V., Tiebout, M.: `A 2 kV ESD-protected 18 GHz LNA with 4 dB NF in 0.13 µm CMOS', ISSCC Dig. Tech. Pprs., February 2008, San Francisco, CA, USA, p. 194–195.
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      • Y.-H. Chen , H.-H. Hsieh , L.-H. Lu . A 24-GHz receiver frontend with an LO signal generator in 0.18-μm CMOS. IEEE Trans. Microw. Theory Tech. , 5 , 1043 - 1051
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      • Yu, T., Rebeiz, G.M.: `A 24 GHz 4-channel phased-array receiver in 0.13 µm CMOS', Proc. RFIC, June 2008, Atlanta, GA, USA, p. 361–364.
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