Low power asynchronous DSP for digital mobile phones
Low power asynchronous DSP for digital mobile phones
- Author(s):
- DOI: 10.1049/ic:20010019
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- Author(s): Source: IEE Seminar Low Power IC Design, 2001 page ()
- Conference: IEE Seminar Low Power IC Design
The CADRE digital signal processor (DSP) architecture is presented. This DSP is intended for use in digital mobile phones and, in this application, it is necessary to balance the requirement of high processing throughput with the demand of low power for extended battery lifetime. These requirements are addressed by a multi-level power reduction strategy, involving the use of a parallel asynchronous architecture, a configurable compressed instruction set, a large register file, the use of sign-magnitude arithmetic, and reduced support for interrupts. (6 pages)
Inspec keywords: low-power electronics; parallel architectures; telephone sets; asynchronous circuits; digital signal processing chips; cellular radio; instruction sets; digital arithmetic
Subjects: Digital arithmetic methods; Mobile radio systems; Digital signal processing chips; Microprocessors and microcomputers; Telephone stations; Parallel architecture
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