Low-power synthesis flow for regular processor design
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- Author(s): R. Woods 1 ; G. Lightbody 1 ; A. Cassidy 1 ; G. Keane 1 ; J. Spanier 1
- Conference: IEE Seminar Low Power IC Design
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Source:
IEE Seminar Low Power IC Design,
January 2001
page
12
Affiliations:
1:
Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast
, UK
The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits for data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative “low-power” project involving the universities of Liverpool Manchester and Sheffield. The design flow is briefly described and some results are presented for multiplier implementations and their use in the development of a discrete cosine transform (DCT) circuit. (5 pages)
Inspec keywords: logic CAD; multiplying circuits; circuit CAD; discrete cosine transforms; integrated circuit design; digital signal processing chips; low-power electronics
Subjects: Digital circuit design, modelling and testing; Semiconductor integrated circuit design, layout, modelling and testing; Microprocessors and microcomputers; Computer-aided circuit analysis and design; Digital signal processing chips; Numerical analysis; Electronic engineering computing; Computer-aided logic design; Integral transforms in numerical analysis; Integral transforms in numerical analysis
