A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
- Author(s):
- DOI: 10.1049/ic:20010017
For access to this article, please select a purchase option:
Buy conference paper PDF
Buy Knowledge Pack
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
Thank you
Your recommendation has been sent to your librarian.
- Author(s): Source: IEE Seminar Low Power IC Design, 2001 page ()
- Conference: IEE Seminar Low Power IC Design
Inspec keywords: asynchronous circuits; carrier mobility; circuit simulation; logic simulation; adders; MOS logic circuits; integrated circuit design; logic CAD; timing; silicon-on-insulator; capacitance; low-power electronics
Subjects: Computer-aided logic design; Other MOS integrated circuits; Electronic engineering computing; Computer-aided circuit analysis and design; Semiconductor integrated circuit design, layout, modelling and testing; Digital circuit design, modelling and testing; Logic and switching circuits; Logic circuits; Metal-insulator-semiconductor structures