In multilevel interconnection, TiSi₂ had been the main SALICIDE material until the mass production of 0.18 μm generation devices. For more advanced devices, CoSi₂ and NiSi are gaining in importance. Consecutively deposited poly-Si and WSi_X POLYCIDE will continue to be used in many deep sub-micrometre devices. With the introduction of low-k dielectric, the processing temperature for PVD is expected to be lowered. This will become a challenge for Al-plug and planarisation processes. It is therefore imperative to develop a low-temperature PVD process. Copper wiring processing having a wide operating range without copper contamination into the bulk silicon during CVD, CMP and RIE will be necessary for many applications. The introduction of copper wiring to ULSIs will begin with the logic ULSIs used in microprocessor and similar devices that require super high speed, and will then be extended to memory ULSIs.

The Co salicide process technology has been applied to CMOS ULSI front-end of line fabrication as a substitute for the Ti salicide process. In order to form thin Co silicide films with low resistivity for CMOS transistor active area, several Co salicide process technologies have been developed. Since, the Co deposition process suffers from poor reproducibility, various Co salicide formation processes have been proposed such as a high temperature Co single layer sputtering followed by in situ vacuum annealing and the bilayer processes with Ti or TiN capping. Consequently, the Co salicide process technology has been successfully introduced to mass production of CMOS ULSIs in several technology generations from 180 to 65 nm.

This book section discusses the growth methods for β-FeSi₂ namely, reactive deposition epitaxy (RDE) and ion beam synthesis (IBS), and describes the physical, optoelectronic, and thermoelectric characteristics of β-FeSi₂. The study presents structure properties of the precipitate as well as the effects of stress on the illuminating characteristics of β-FeSi₂ including sources of stress, using Raman optical measurement to obtain the stress values, and effect of stress on the feature of β-FeSi₂. The optical properties are discussed through photoluminescence and electroluminescence measurement studies, also focusing on the effect of annealing on photoluminescence.

In this chapter, the silicon-on-insulator (SOI) silicide technologies are described starting from the review of silicide design analysis on SOI, including the effects of source/drain series resistance and gate resistance on SOI device performance, the silicide thickness design analysis, and silicon resistivity design space for a specific design constraint. The dominant parameters for silicidation on SOI devices are the silicide/Si specific contact resistivity, the silicide thickness, and the silicon resistivity. Both the interface-specific contact resistivity and the silicon resistivity are directly related to the dopant concentration in the silicon layer. To minimise these resistivities, the degenerate doping in the source/drain regions is needed to be minimised to the order of 10²⁰ cm^-3. The challenges to implement existing bulk silicide technology to SOI devices are introduced which include titanium silicide process and voids, silicide thickness control, and thin silicide thermal stability. Finally, various silicide technologies on SOI including pre-amorphisation source/drain regions to control silicide depth, cobalt and nickel silicide technology for thin film SOI devices, low-barrier silicides of ErSi₂ and PtSi for sub-20 nm novel devices, as well as selective silicide deposition on SOI, are discussed.

This appendix is a glossary of electronic engineering terms.